Interconnection of Godson-3 Multi-Core Processor

The interconnection of Godson-3 multi-core processor adapts a 2D mesh based scalable distributed architecture, providing unified topology for chip level, board level, and system level design. HyperTransport protocol is implemented in Godson-3, both for IO connection and multi-chip interconnection. Software configurable routing arithmetic could provide efficient communication for board level CC-NUMA system or the NCC-NUMA system on a larger scale. Introduced in this paper the interconnecting network of Godson-3 multi-core processor. On the chip level, two-level scalable architecture is implemented inside Godson-3: a 2D mesh is used to connect all the nodes in the top level; two crossbars are used inside every node to connect 4 cores and 4 L2 caches, along with memory controllers and IO controllers. On the board level, the medium scale multi-chip system of CC-NUMA can be easily constituted by using cache coherence protocol supported HyperTransport interface interconnection. A larger scale multi-chip system can be constituted by using dedicated hardware for networking. Based on all these architectural supports, it becomes much easier to constitut an efficient and scalable shared memory multi-chip system.