A Low-Power High-Performance Sliding Cache Scheme

Cache memories account for a significant fraction of a chip’s overall energy dissipation. Recent researches advocate using “resizable” caches to exploit cache requirement variability in applications would reduce cache size and eliminate energy dissipation in the cache’s unused sections with minimal impact on performance. Based on the fact that different programs need different sizes of instruction and data cache, a novel sliding cache structure is proposed. This scheme can dynamically adjust the configuration of level 1 cache by balancing the instruction and data cache requirement. SPEC95 simulation results indicate that the dynamic power and static leakage power of level 1 cache can be reduced using sliding cache structure. Meanwhile, the dynamic power of microprocessor is decreased and the performance of microprocessor is improved. Compared with the two conventional cache structures and DRI structure, the average dynamic power of level 1 cache with sliding cache structure is reduced by 21.3%, 19.52% and 20.62% respectively. Microprocessor with sliding cache structure exhibits decreases of 8.84%, 8.23% and 10.31% of the average dynamic power reduction, while its energy delay production improves 12.25%, 7.02% and 13.39% compared with the two traditional cache structures and DRI structure.