A STUDY OF THE COMPILER-DIRECTED LOW POWER MULTITHREADING TECHNOLOGY

Multithreading and low power is one of the main goals to be studied, solved and realized for next generation micro architecture. A power model based on SMT （simultaneous multithreading） architecture for scaling the dynamic frequency of function units to decrease the CPU power/energy consumption is proposed in this paper. Further more, how to recognize the regions being possible for scaling the execution frequency at compile time is analyzed and discussed, the models for computing the scaling frequency and analyzing the energy consumption are given also, and then the compile policy is proposed. The goal is to save more significant power/energy without an apparent degradation in performance. In theory, this model can also be used to superscalar and multiprocessor architectures.