Research and Implementation of an Optimizing Design Method of De-Synchronized Circuit

De-synchronous design method, which is compatible with the traditional EDA tools, can greatly improve the design efficiency and decrease the design difficulties of asynchronous circuits. An optimizing design method of de-synchronous circuit based on an abstract model called control graph is presented in this paper. Control graph is an abstract model of de-synchronous circuit. The core step of this optimizing design method is to combine the local controllers in the control path, and a proof has also been given that this combining procedure can preserve the functional equality of this circuit. Through this design method, the area of the control path can be markedly reduced. This optimizing design method takes the performance evaluation function as its heuristic function, so there is not any penalty on performance. Because this optimizing problem is an NP-hard problem, an approximate algorithm is introduced. To demonstrate the results of this algorithm, it has been applied to a set of benchmark circuits. According to the results, the number of local controllers is decreased 54%, and 76.3% of C-elements required to construct handshake circuit are removed. Finally, a 32-bits de-synchronous multiplier in 0.35μm process is designed with this optimizing design method. Compared with the traditional design method of de-synchronous circuit, this optimizing design method will lead to smaller circuit without any penalty in performance.