Power Analysis Attacks Against AES Based on Maximal Bias Signal

Any circuit implementation of a cryptographic system might cause power leakages to reveal more information about the processed secret. A new way is proposed to enhance power analysis attacks on AES circuit implementations. The proposed method adopts Hamming difference of intermediate results as power model and arranges plaintext inputs to maximize the difference of power traces in order to retrieve the key value. Using UMC 0.25μm 1.8v technology library and Synopsys EDA tools, a simulation-based power acquisition environment is set up. On the simulation-based platform, various power attacks are conducted on AES circuit implementation. As the partitioning criterions of single-bit and multi-bit differential power analysis (DPA) are usually abstract and simple, these two DPA methods can not retrieve any useful information even with 6000 power measurements. Although the correlation power analysis (CPA) attack can extract the right subkey based on 4000 power measurements, its computational complexity sometimes exhibits a bottle-neck. Experimental results show that the proposed method improves the success rate effectively using acceptable power measurements. Furthermore, the proposed DPA traces can be built through simple summing and subtracting operations instead of complex statistic techniques. Therefore, compared with the original DPA and CPA attacks, the presented DPA approach excels them in both effectiveness and computation requirements.