Optimization of Two Dimensional Test Data Compression

In order to reduce the storage volume of test data during the built-in self-test (BIST), based on the two dimensional test data compression BIST scheme which combines input reduction (horizontal compression) and TRC test set embedding (vertical compression), the improved input reduction algorithm and TRC seed selection algorithm based on compatibility judging are utilized simultaneously to optimize the horizontal and vertical compression. The optimization includes the influence of percentage of specified bits (PSB) on the vertical compression under the same percentage of compatibility (PC), and the influence of PC on the vertical compression under the same PSB. Experimental results for ISCAS89 benchmark circuits show that there is always a range of PC ［PC\-low_limit，PC\-high_limit］ which makes the test storage minimal for each PSB, and the relationships between PSB and PC\-low_limit and PC\-high_limit are linear. The proposed two dimensional compression scheme requires 20%~75% less test storage compared with the previous test data compression schemes, and it is indeed possible to embed the entire precomputed test set in TRC sequence. Furthermore, the test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Finally, the proposed approach requires no mapping logic gates between the test generator circuit and the CUT; hence it imposes no additional performance penalty.