A Novel Flow for Asynchronous Circuit Design Using Synchronous EDA Tools

With the rapid development of VLSI technology and the great increase of application requirements, the synchronous circuit with global clock has encountered several crucial problems, such as great clock skew and high power dissipation. Heightened interest in low power consumption and growing concern over clock skew have encouraged the use of asynchronous techniques as a viable approach to future circuit design. But the wide acceptance of asynchronous circuits has been hindered by the lack of commercial EDA tools. Since current design methodologies are difficult for VLSI design and implementation, a novel design flow for asynchronous circuits is presented. By fully using conventional EDA tools, this flow can improve the efficiency and decrease the difficulties of design as well. To obtain optimized circuit structure, multi-virtual clock method is used for logic synthesis. The delay of asynchronous control path is also accurately matched through a quantitative analysis approach. Based on this flow, an asynchronous microprocessor core in UMC 0.18μm process is designed and implemented. Experimental results show that this flow can make the design of asynchronous circuits easily and effectively, and the asynchronous circuit style can offer a low power solution for future microprocessor design.