An Optimized Code-Generating Algorithm for Reconfigurable Instruction Set Processors

Reconfigurable instruction set processors (RISP) can adapt to the requirements of both performance and flexibility for various applications. However, traditional compiling technology cant fit to generate efficient executable codes for them and it needs a new code-generating method for compilers. This paper presents a mixed code-generating algorithm based on the extension of the traditional three-step method in compilation. The algorithm makes the best reuse of the traditional method and generates the optimized binary codes for dynamically extended reconfigurable instructions according to the reconfigurable resources and configuration. The algorithm can obtain executable codes which are appropriate for the characteristics of the object architecture. The experiments demonstrate that the algorithm is effective for the hardware reconfiguration with the instruction codes, and it can enhance the performance of the application running on the new platform.