Analysis of Inter-Thread Interference on Shared Cache Multi-Core Architectures Based on Instruction Fetch Timing Frame

In real-time systems, designers need to obtain a safe and tight worst-case execution time (WCET) of applications. It is very challenging for multi-core processors due to the possible inter-thread interference caused by shared resources. For multi-core platforms with shared caches, instructions may be evicted by another co-running thread, which results in inter-thread interference in shared cache. In this case the execution time of applications can not be analyzed independently. The inter-thread interference should be taken into consideration in WCET analysis on multi-core platforms. This paper proposes a sufficient and unnecessary condition of non-interference to analyze the worst-case inter-thread interference by considering the timing frame of instruction fetch. Our approach introduces the consideration of timing frames into the conservative address analysis. Therefore, the worst-case shared cache misses can be reasonably estimated to determine the latency of inter-thread interference in shared cache. Our experiments indicate that the proposed approach improves the tightness of WCET estimation by 12% as compared with the representative related work which proposes an lifetime-based method, and by 7% as compared with another representative related work which is based on the structure order of shared cache accesses.