FPGA DESIGN FOR A BAR CODE PREPROCESSOR BASED ON VHDL HIGH LEVEL SYNTHESIS

The function definition of a bar code preprocessor and its behavior description with VHDL are presented.Starting from the description of the algorithmic level behavior,the FPGA oriented top down design procedure of a bar code preprocessor is studied,which is based on the VHDL high level synthesis system HLS/BIT.It is shown that the combination of VHDL high level synthesis and FPGA can simplify the complexity and increase the efficiency in ASIC design.