Design-for-Testability and Test Technologies for System-on-a-Chip

A comprehensive survey of the up-to-date design-for-testability(DFT) methods and testing technologies for system-on-a-chip(SOC) is presented. The techniques of DFT and testing for embedded cores of digital, analog/mixed-signal, memory and processor are introduced respectively. Among these techniques, some advanced scan and built-in-self-test schemes to provide at-speed test capability or to reduce test application time, test power consumption and test data volume are emphasized. The DFT and testing techniques for SOC at system level are also surveyed. Since test resources are very important to cope with new issues of testing SOC, design, partitioning and optimization of test resources are described in detail. In an SOC, on-chip test resources generally include test access mechanism, test wrapper, and test source and sink. For test source and sink, test resource partitioning approaches based on test stimuli compression/decompression and test response compaction are overviewed. For test access mechanism and test wrapper, test resource optimization techniques of test scheduling based on heurist algorithms are presented. The SOC test standardization by two organizations is introduced. Finally, some future directions in DFT and test technologies for SOC are indicated, and an extensive bibliography is also provided.