XU Xiulan. A New Method of Generating Test Pattern in VLSI Circuits Built-in Self-Testing TechniquesJ. Journal of Computer Research and Development, 1993, 30(11): 61-66.
Citation:
XU Xiulan. A New Method of Generating Test Pattern in VLSI Circuits Built-in Self-Testing TechniquesJ. Journal of Computer Research and Development, 1993, 30(11): 61-66.
XU Xiulan. A New Method of Generating Test Pattern in VLSI Circuits Built-in Self-Testing TechniquesJ. Journal of Computer Research and Development, 1993, 30(11): 61-66.
Citation:
XU Xiulan. A New Method of Generating Test Pattern in VLSI Circuits Built-in Self-Testing TechniquesJ. Journal of Computer Research and Development, 1993, 30(11): 61-66.
A New Method of Generating Test Pattern in VLSI Circuits Built-in Self-Testing Techniques
A new method of on chip tert pattern in buit-in selt-terting formed by a binary Counter and XOR gates is discussed.The designed array can be simplified with linear algebraic synthesis By this approach,a Considerable limited hardware can achieve a good fault coverage and promote the applatiicon of built-in self-testing technique.
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