THE FEIG FAST DCT ALGORITHM AND ITS PROCESSOR ARCHITECTURE DESIGN

Discrete cosine transform（DCT） is a key element in the JPEG and MPEG standards. The current and projected popular usage of MPEG is for decoding applications. An example of decoding application is the video\|CD（VCD） in which inverse discrete cosine transform（IDCT） is a key element for the decompression of still/motion\|compensated video frames. It is indicated that IDCT embedded in products is performed by hard\|wired logic for performance reason. The approach has the drawback that the hard\|wired logic cannot help in other functionalities required in MPEG such as audio decoding, variable length decoding of video/audio bit stream, etc.. It is proposed that by executing the very efficient Feig IDCT algorithm using a processor architecture that performs parallel execution of sequential instruction streams, the above MPEG requirements can be satisfied. The proposed processor requires less hardware resources than the dedicated hard\|wired approach and the surplus computational power can also be used for audio decoding and variable length decoding of video/audio bit streams, etc..