Two Condition Code Optimization Approaches in Binary Translation

It is an important performance issue how to reduce the emulation cost of the source Instruction Set Architecture's condition codes. In this paper, two optimized emulating algorithms for emulator and dynamic translator are presented, which can effectively improve the performance of the translated code. In emulator, ICDC(instant computing and delayed computing) algorithm compared with delay computing algorithm, can reduce the memory access overhead of object code. In dynamic translator, DFADC(data flow analysis and delayed computing) algorithm is presented to reduce redundant flag computing code. Data flow analysis is used in basic block, and delayed computing is used inter basic block. The two new optimized emulating algorithms can be applied in all the translation from source ISA with flag mechanism to target ISA without such mechanism. These algorithms are verified in the binary translator system——Digital Bridge, which combines emulation and dynamic translation methods. With these algorithms, Digital Bridge can do binary translation in 120% code size of the original binary code, while it could be 250% code size for non-optimized algorithms and 150% code size for UQDBT system. These data indicate that the algorithms are effective to reduce redundant code and to improve the performance of translated code.