Design and Implementation of a Memory Model Simulator

Cache coherence and memory consistency are two important problem to a shared memory parallel computer. Many coherence protocol and consistency model have been proposed for different systems. Simulation is a quantitative approach to compare different consistency model and coherence protocol. This paper gives a scheme and implementation of a shared memory model simulator—MMS. First the framework of the simulator is described. MMS includes an execution engine and a virtual shared memory system. The engine can execute parallel threads and simulate the behavior of shared memory system. Several memory consistency models are realized, such as sequential consistency model, weak consistency model, release consistency model and lazy release consistency model. Then different memory consistency models, including SC, WC, RC and LRC, are compared between different parallel computer architecture models, including SMP and DSM. The behavior of different memory consistency models is also simulated in solving different type computing problem, including computing intensive problem, communication intensive problem and memory intensive problem. To achieve high performance several cache coherence protocols are proposed. Finally it is concluded that for different computer architectures, proper memory consistency model and proper cache coherence protocol should be employed.