Software Simulation for Hardware/Software Co-Verification

With the development of integrated circuits and computer science, software and hardware of the target system become more and more sophisticated while the traditional methods of the embedded system design appear to be outdated. For complicated embedded systems, co-verification is often used to verify the system co-design, in which hardware simulator based on hardware specification is used to validate the hardware design while the processor architecture model known as instruction set simulator (ISS) is used to interpret the target code of the embedded software, generate output, and drive the hardware. The ISS simulates the embedded software at detailed timing level for the target processor, simulating at such a low-level that it often becomes the bottleneck for hardware/software co-simulation. In this paper, a fast software simulating method is put forward, in which, an open-source RTOS is extended and hardware-simulating driver is used to build connection for the hardware/software simulator. The simulating method based on the compiled code model for the embedded software verifies the software from the system behavior level, so higher co-verification performance can be achieved. Combined the with verification method of ISS, the high-level co-verification method can achieve faster and more effective co-verification. Finally, examples of co-design and results of co-verification are presented to show the correctness of the co-verification method.