ZHU Ming, TENG Hong, SHI Weisong, TANG Zhimin. DESIGN AND TEST OF A HIGH SPEED PRNS DIGITAL FULL ADDERJ. Journal of Computer Research and Development, 1998, 35(3).
Citation:
ZHU Ming, TENG Hong, SHI Weisong, TANG Zhimin. DESIGN AND TEST OF A HIGH SPEED PRNS DIGITAL FULL ADDERJ. Journal of Computer Research and Development, 1998, 35(3).
ZHU Ming, TENG Hong, SHI Weisong, TANG Zhimin. DESIGN AND TEST OF A HIGH SPEED PRNS DIGITAL FULL ADDERJ. Journal of Computer Research and Development, 1998, 35(3).
Citation:
ZHU Ming, TENG Hong, SHI Weisong, TANG Zhimin. DESIGN AND TEST OF A HIGH SPEED PRNS DIGITAL FULL ADDERJ. Journal of Computer Research and Development, 1998, 35(3).
DESIGN AND TEST OF A HIGH SPEED PRNS DIGITAL FULL ADDER
Based on the research of references and , a new 336 ary PRNS digital adder is designed successfully by using the waver pipelining principle, and is implemented very well with relational F100K chips. Finally, the results of functional testing show that its clock is up to 7ns.
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