Low Power Design of a Data Buffer

The design and function of a data buffer of LS MPP co processor designed in "Ninth Five Year Plan" is introduced first Then a novel method to reduce its power dissipation and its I/O pads is put forward Finally a new scheme of the data buffer is proposed It can be assured that only one PE’s data buffer is active when the PE array exchanges data with the external memory As a result, the power dissipation is reduced to one N×Nth, and is dependent of the scales of PE array