THE INFLUENCE OF EMBEDDED MEMORY ON ATPG IN SOC DESIGN

In ASIC design, SoC （systems-on-a-chip） has been used more and more frequently. Meantime chip design and test become more complex due to the integration of embedded IP cores and embedded memories. Especially, in ATPG these units have significant influence on fault coverage. Some methods have been developed in the testing memory, but generally they do not consider the influence of embedded memory on the testability of surrounding logic. After analyzing the influence of embedded memory on ATPG, an RTL level DFT method is proposed to eliminate the problem. The effectiveness of the method has been proved by experiment.