BOOLEAN PROCESS-BASED HIERARCHICAL DELAY ANALYSIS

The design of complex and high speed chips imposes new requirements on the exact timing characterization of circuits. The delay of a circuit depends not only on its topological structure, but also on its functionality and the inputs. Boolean process, which describes the functionality and the timing behavior of a circuit in a united analytical form, is the basis of the paper. The concept of sensitization by partial derivative of waveform polynomial is redefined. The analytical delay model is improved with the new concept of sensitization. A delay matrix model of leaf circuits is built based on the longest sensitizable path, from which an exact hierarchical delay analysis approach is derived. Finally, the efficiency of the proposed method is proved by experiments.