A METHOD OF DECREASING DATA WIDTH BETWEEN CACHE AND SYSTOLIC ARRAY ON MOTION ESTIMATION CHIP

Aiming at cache design, which plays an important role in motion estimation（ME） chip, a design method of decreasing data width between cache and systolic array, which simplifies design of cache control. Two new architectures on AB2 and AS2 are constructed by using the novel method. Decreasing the port number will bring about the problem of low efficiency. A formula which shows connection between port number and computing time can give a tradeoff. The research result coming from the work of ME chip’s realization, is beneficial to the work of studying MPEG 2’ encoder.