A WIRE SIZING ALGORITHM FOR DELAY AREA BALANCED CLOCK ROUTING

The wire sizing method is an efficient solution to the interconnect optimization under deep submicron technology. In this paper, a multi phase wire sizing algorithm is brought forward to optimize delay, area, and clock skew. First, a sensitivity based algorithm is proposed to optimize the delay of the clock tree. Then an approximate programming is used to solve the area minimization. Finally, some branches width can be resized to reduce skew further. It is shown experimentally that the algorithms presented can solve efficiently the optimization of delay, area, and skew, and the efficiency and accuracy are satisfactory.