A Fast Floating-Point Multiplier Architecture

A floating-point multiplier, supporting IEEE 754 standard and fully pipelined, is presented. A new architecture style of two-way multiplier is proposed. It can reduce 13.6% delay of critical path of an adder tree without increasing the area of the multiplier according to the full size multiplier. The overall multiplier has a latency of 3 cycles and a throughput of 1 cycle for a single-precision or double-precision floating-point instruction. This multiplier has been verified in FPGA and implemented in 0.18 micron standard cell technology, with its frequency being 384MHz and its area 732902.25μm 2. This architecture is compared with some other architectures using the same technique, and the result shows that it is effective and efficient.