Leakage Power Simulator of CMOS Circuit Under DSM Process

As technology evolves, power dissipation has become a critical issue of VLSI circuit design Lowering power supply voltage is an efficient method to reduce dynamic power In order to maintain performance, the threshold voltage of a device should be reduced accordingly, which results in an exponential increase of static power When entering into deep sub micron （DSM） process era, leakage power becomes comparable with dynamic power consumption Fast simulators are urgently needed just as are low leakage design technologies Precise circuit simulators （such as HSPICE） can accurately account for leakage power estimation, but are only practical for small circuits Firstly, in this paper, the stack effect of CMOS transistors and primitive logic gates is demonstrated based on which a leakage model of the simulator is put forward And then experiments on ISCAS?85＆89 benchmark circuits are given to show this simulator is hundredfold accelerated compared with HSPICE with endurable accuracy （error under 3%）, the memory explosion problem of accrate simulator is also solved in the same time