DESIGN OF SCAN-BASED LOW TESTING POWER ARCHITECTURE

Area, power and testability are three important facts in the optimization of VLSI circuits. The cost of test is increasing because the scale of integrated circuits is getting higher and higher. Scan-based techniques of design for testability are widely implemented in VLSI circuits to improve their testability, although trade off is needed for area, performance and power. A novel scan-based technique taking into account the testing power is presented in this paper. Measured result shows it has the advantage of testing power reduction, while the cost of area and testing time are limited.