Research on Register Requirements of Software Pipelined Loops in the IA-64 Architecture

Software pipelining is a loop scheduling technique that extracts instruction level parallelism by overlapping the execution of several consecutive iterations. IA-64 is a new EPIC architecture that provides hardware support on software pipelining. The register requirements of software pipelined loops are evaluated, and a new heuristic algorithm is proposed to restrict unrolling factor. Experimental results show that the new algorithm increases the number of software pipelined loops and improves the performance of compiler.