DESIGN AND PERFORMANCE ANALYSIS OF THE INSTRUCTION FETCH UNIT IN JE JAVA CHIP

In the first section of this paper, the design of JE Java chip’s instruction fetch unit is introduced. According to the performance analysis with the two methods of analysis model and simulation, an optimized set of system parameters and instruction pre fetch strategy are gained. It is shown that the results of the above two methods tally with the real ones of the JE Java chip.