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Wang Chong, Wei Shuai, Zhang Fan, Song Ke. A Survey of Cache-Based Side Channel Countermeasure[J]. Journal of Computer Research and Development, 2021, 58(4): 794-810. DOI: 10.7544/issn1000-1239.2021.20200500
Citation: Wang Chong, Wei Shuai, Zhang Fan, Song Ke. A Survey of Cache-Based Side Channel Countermeasure[J]. Journal of Computer Research and Development, 2021, 58(4): 794-810. DOI: 10.7544/issn1000-1239.2021.20200500

A Survey of Cache-Based Side Channel Countermeasure

Funds: This work was supported by the National Science and Technology Major Projects of Hegaoji (2017ZX01030301).
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  • Published Date: March 31, 2021
  • Microarchitectural side channel attack uses microarchitecture state to stole information from victim. It breaks the isolation offered by operation system, sandbox and so on, which seriously threatens information security and private, thus it receives extensive attention from academia. Unlike other traditional side channel attacks, microarchitectural side channel attack doesn’t require physical contact, nor complex analysis device, and it only needs co-run some code with victim in some share resources. Cache-based side channel attack uses cache such as private L1 Cache and LLC (last level cache) to learn the access pattern of other application, and uses this access pattern to infer secrets. Owning to the fact that cache is widely used in modern CPU, cache-based side channel attack is the most attractive attacks. It’s still an open challenge to defense this kind of attack. In this paper, we firstly introduce the basic architecture and theory related with microarchitectural side channel especially cache-based side channel attack. Then, we consolidate existing attack methods into an attack model from attacker ability, attack steps and attack target. According to this model, we classify types of the main existing countermeasure to cache-based side channel attack, and focus on the design of the new secure cache architecture. Finally, we present the trends in countermeasure, challenge to combating them and future directions especially new cache architecture.
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