Liu Chaojie, Wang Fang, Zou Xiaomin, Feng Dan. A Scalable Timestamp-Based Durable Software Transactional Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 499-517. DOI: 10.7544/issn1000-1239.20210565
Citation:
Liu Chaojie, Wang Fang, Zou Xiaomin, Feng Dan. A Scalable Timestamp-Based Durable Software Transactional Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 499-517. DOI: 10.7544/issn1000-1239.20210565
Liu Chaojie, Wang Fang, Zou Xiaomin, Feng Dan. A Scalable Timestamp-Based Durable Software Transactional Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 499-517. DOI: 10.7544/issn1000-1239.20210565
Citation:
Liu Chaojie, Wang Fang, Zou Xiaomin, Feng Dan. A Scalable Timestamp-Based Durable Software Transactional Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 499-517. DOI: 10.7544/issn1000-1239.20210565
(Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074)
Funds: This work was supported by the National Key Research and Development Program of China (2018YFB1003305), the Key Program of the National Natural Science Foundation of China (61832020), and the Foundation for Innovative Research Groups of the National Natural Science Foundation of China (61821003).
The emerging non-volatile memory(NVM) provides a lot of advantages, including byte-addressability, durability, large capacity and low energy consumption. However, it is difficult to perform concurrent programming on NVM, because users have to ensure not only the crash consistency but also the correctness of concurrency. In order to reduce the development difficulty, persistent transactional memory has been proposed, but most of the existing persistent transactional memory has poor scalability. Through testing, we find that the limiting factors of scalability are global logical clock and redundant NVM write operation. In order to eliminate the impact of these two factors on scalability: A thread logical clock method is proposed, which eliminates the problem of global logical clock centralization by allowing each thread to have an independent clock; a dual version method of cache line awareness is proposed, which maintains two versions of the data, and updates the two versions cyclically to ensure the crash consistency of the data, thereby eliminating redundant NVM write operations. And based on these two methods, a scalable durable transactional memory (SDTM) is implemented and fully tested. The results show that under YCSB workload, compared with DudeTM and PMDK, its performance is up to 2.8 times and 29 times higher, respectively.