Pei Songwen, Qian Yihuan, Ye Xiaochun, Liu Haikun, Kong Linghe. DRAM-Based Victim Cache for Page Migration Mechanism on Heterogeneous Main Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 568-581. DOI: 10.7544/issn1000-1239.20210567
Citation:
Pei Songwen, Qian Yihuan, Ye Xiaochun, Liu Haikun, Kong Linghe. DRAM-Based Victim Cache for Page Migration Mechanism on Heterogeneous Main Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 568-581. DOI: 10.7544/issn1000-1239.20210567
Pei Songwen, Qian Yihuan, Ye Xiaochun, Liu Haikun, Kong Linghe. DRAM-Based Victim Cache for Page Migration Mechanism on Heterogeneous Main Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 568-581. DOI: 10.7544/issn1000-1239.20210567
Citation:
Pei Songwen, Qian Yihuan, Ye Xiaochun, Liu Haikun, Kong Linghe. DRAM-Based Victim Cache for Page Migration Mechanism on Heterogeneous Main Memory[J]. Journal of Computer Research and Development, 2022, 59(3): 568-581. DOI: 10.7544/issn1000-1239.20210567
1(School of Optical-Electrical and Computer Engineering, University of Shanghai for Science and Technology, Shanghai 200093)
2(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190)
3(School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan 430074)
4(Department of Computer Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240)
Funds: This work was supported by the National Natural Science Foundation of China (61975124), the Shanghai Natural Science Foundation (20ZR1428600), the Shanghai Science and Technology Innovation Action Plan (20DZ2303500, 20DZ2308700, 19DZ2301100), the Open Project Program of Shanghai Key Laboratory of Data Science (2020090600003), and the State Key Laboratory of Computer Architecture (ICT, CAS) (CARCHA202111).
When massive data access heterogeneous memory systems, memory pages often migrate between DRAM and NVM. However, the traditional memory page migration strategy is difficult to adapt to the rapid dynamic changes among “hot” and “cold” memory pages. The “cold” pages just migrated from DRAM to NVM will become “hot” again, which results in a large number of redundant migrations, as well as false migrations. Previous related researches only focus on pages that are being migrated without paying too much attention to pages that in the migration waiting queue or that have been migrated. Therefore, this paper proposes a heterogeneous memory page migration mechanism based on DRAM-based victim Cache (VC-HMM) by adding a small capacity of victim Cache between DRAM and PCM. The “cold” pages will be migrated from DRAM to victim Cache. DRAM victim Cache can avoid redundant migrations caused by the main memory pages getting hot again in a short time. Meanwhile, some pages do not need to be written back to PCM that can reduce the number of write operations on PCM and extend the lifetime of PCM. In particular, VC-HMM can automatically update the execution parameters of migration for different workloads to increase the rationality of migration. Experimental results show that compared with other migration strategies (CoinMigrator, MQRA, THMigrator), VC-HMM reduces the average number of PCM write operations by 62.97%, the average access latency by 22.72%, the re-migration times by 38.37%, and the energy consumption by 3.40%.
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