Survey of Real-Time Computer System Architecture

Gong Xiaohang; Jiang Binze; Chen Xianglan; Gao Yinkang; Li Xi

doi:10.7544/issn1000-1239.202220731

Journal of Computer Research and Development > 2023 > 60(5): 1021-1036. > DOI: 10.7544/issn1000-1239.202220731

Gong Xiaohang, Jiang Binze, Chen Xianglan, Gao Yinkang, Li Xi. Survey of Real-Time Computer System Architecture[J]. Journal of Computer Research and Development, 2023, 60(5): 1021-1036. DOI: 10.7544/issn1000-1239.202220731

Citation:

PDF (1011 KB)

Survey of Real-Time Computer System Architecture

School of Computer Science and Technology, University of Science & Technology of China, Hefei 230027
Suzhou Institute for Advanced Research, University of Science & Technology of China, Suzhou, Jiangsu 215123

Funds: This work was supported by the National Key Research & Deveolpment Program of China(2017YFA0700900, 2017YFA0700903), the National Natural Science Foundation of China(62102383, 61976200, 62172380), the Jiangsu Provincial Natural Science Foundation(BK20210123), the Youth Innovation Promotion Association CAS(Y2021121), and the USTC Research Funds of the Double First-Class Initiative (YD2150002005).

More Information

Author Bio:
Gong Xiaohang: born in 1999. Master candidate. His main research interest includes computer architecture

Jiang Binze: born in 2000. Master candidate. His main research interest includes computer architecture

Chen Xianglan: born in 1977. PhD. Her main research interest includes system software

Gao Yinkang: born in 1998. Master candidate. His main research interest includes computer architecture

Li Xi: born in 1963. Professor. His main research interest includes computer architecture
Received Date: August 21, 2022
Revised Date: April 03, 2023
Available Online: April 09, 2023

Graphical Abstract

Abstract

Abstract

In time-sensitive embedded systems, tasks need to meet their deadlines, and missing deadlines can significantly affect the quality of service or have catastrophic consequences. Compared with the general system, the research progress of real-time system is slow, even many basic concepts have not reached consensus. Precision timed (PRET) machine and real-time processing unit (RPU) are two existing real-time system solutions. Taking them as examples, we introduce the related concepts of real-time system, expound the problems in the development of real-time system, and compare the similarities and differences. The problems encountered at each level of the real-time system and the existing solutions are analyzed. At the application layer, the user needs an interface for periodic operations; in instruction set architecture (ISA) layer, resources provided by hardware should be fully utilized to provide sufficient semantic abstraction and timing precision to the upper layer. The hardware layer needs to support ISA's time attributes and time semantics, and to improve performance as much as possible while ensuring real-time performance. Research on real-time systems faces many challenges. In the process of designing and researching the existing real-time system, the key problem is that the time semantics of the upper application is difficult to keep consistent with the lower implementation.
- time sensitive system,
- time attribute,
- time semantics,
- real-time machine,
- real-time system solutions

FullText(HTML)

References (60)

References

[1]	Wikipedia. Whirlwind I[EB/OL]. [2022-08-18]. https://en.wikipedia.org-/wiki/Whirlwind_I
[2]	Mitra T, Teich J, Thiele L. Time-critical systems design: A survey[J]. IEEE Design & Test, 2018, 35(2): 8−26
[3]	Roop P. Predictable reactive processors for next generation computing: A proposal[EB/OL]. [2022-05-30]. https://www.researchgate.net/publication/254356051
[4]	Andalam S, Roop P, Girault A, et al. PRET-C: A new language for programming precision timed architectures[J/OL]. Inria, 2009[2022-08-18].https://hal.inria.fr/inria-00391621
[5]	Edwards S A, Lee E A. The case for the precision timed (PRET) machine[C]//Proc of the 44th Annual Design Automation Conf. New York: ACM, 2007: 264−265
[6]	汪超, 陈香兰, 章博, 等. 一种具有时间语义的实时处理器模型[J]. 计算机研究与发展, 2021, 58（6）: 1176−1191 Wang Chao, Chen Xianglan, Zhang Bo, et al. A real-time processor model with timing semantic[J]. Journal of Computer Research and Development, 2021, 58(6): 1176−1191 (in Chinese)
[7]	Stankovic J. Misconceptions about real-time computing: A serious problem for next-generation systems[J]. Computer, 1988, 21(10): 10−19 doi: 10.1109/2.7053
[8]	Lee E A. What is real time computing? A personal view[J]. IEEE Design & Test, 2018, 35(2): 64−72
[9]	Laplante P A, Ovaska S J. Real-Time Systems Design and Analysis: Tools for the Practitioner[M]. 4th ed. Piscataway, NJ: IEEE, 2011
[10]	Cheng A M K. Real-Time Systems: Scheduling, Analysis, and Verification[M]. Piscataway, NJ: IEEE, 2011
[11]	Thiele L, Wilhelm R. Design for timing predictability[J]. Real-Time Systems, 2004, 28(2): 157−177
[12]	Kirner R, Puschner P. Time-predictable computing[C]//Proc of the Software Technologies for Embedded and Ubiquitous Systems. Berlin: Springer, 2010: 23−34
[13]	Cullmann C, Ferdinand C, Gebhard G, et al. Predictability considerations in the design of multi-core embedded systems[C]//Proc of Embedded Real Time Software and Systems. Toulouse, France: Association Aéronautique et Astronautique de France, 2010: 36−42
[14]	Davis R I, Burns A. A survey of hard real-time scheduling for multiprocessor systems[J]. ACM Computing Surveys, 2011, 43(4): 1−44
[15]	Wilhelm R, Engblom J, Ermedahl A, et al. The worst-case execution-time problem —Overview of methods and survey of tools[J]. ACM Transactions on Embedded Computing Systems, 2008, 7(3): 1−53
[16]	Zhuravlev S, Saez J C, Blagodurov S, et al. Survey of scheduling techniques for addressing shared resources in multicore processors[J]. ACM Computing Surveys, 2012, 45(1): 1−28
[17]	Lee E, Reineke J, Zimmer M. Abstract PRET machines[C]//Proc of the 2017 IEEE Real-Time Systems Symp(RTSS). Piscataway, NJ: IEEE, 2017: 1−11
[18]	Liu I. Precision timed machines[D]. Berkeley, CA: University of California, Berkeley, 2012
[19]	Reineke J, Liu I, Patel H D, et al. PRET DRAM controller: Bank privatization for predictability and temporal isolation[C]//Proc of the 9th IEEE/ACM/IFIP Int Conf on Hardware/Software Codesign and System Synthesis (CODES+ISSS). New York: ACM, 2011: 99−108
[20]	Zimmer M, Broman D, Shaver C, et al. FlexPRET: A processor platform for mixed-criticality systems[C]//Proc of the 19th IEEE Real-Time and Embedded Technology and Applications Symp. Piscataway, NJ: IEEE, 2014: 101−110
[21]	Halbwachs N. Synchronous Programming of Reactive Systems[M]. Berlin: Springer, 1998: 1−16
[22]	陈香兰,李曦,汪超,等. 实时机模型及时间语义指令集研究[J]. 计算机工程与科学,2021,43(4):571−578 doi: 10.3969/j.issn.1007-130X.2021.04.001 Chen Xianglan, Li Xi, Wang Chao, et al. Research on real-time machine model and instruction set with time semantics[J]. Computer Engineering and Science, 2021, 43(4): 571−578 (in Chinese) doi: 10.3969/j.issn.1007-130X.2021.04.001
[23]	Cloudflare, Inc. μC/OS-II[EB/OL]. [2022-08-18]. https://www.osrtos.com/rtos/uc-os-ii
[24]	Amazon Web Services. FreeRTOS[EB/OL]. [2022-08-18]. https://www.freertos.org
[25]	Network Solutions, LLC. RTEMS[EB/OL]. [2022-08-18]. https://www.rtems.org
[26]	汪超. 时间可预测计算机体系结构研究[D]. 合肥: 中国科学技术大学, 2022 Wang Chao. Research on time-predictable computer architecture[D]. Hefei: University of Science and Technology of China, 2022 (in Chinese)
[27]	李曦, 陈香兰, 王超, 等. 实时嵌入式系统设计方法[M]. 北京: 清华大学出版社, 2022 Li Xi, Chen Xianglan, Wang Chao, et al. Design Method of Real-Time Embedded System[M]. Beijing: Tsinghua University Press, 2022(in Chinese)
[28]	Wägemann P, Distler T, Eichler C, et al. Benchmark generation for timing analysis[C]//Proc of the 2017 IEEE Real-Time and Embedded Technology and Applications Symp(RTAS). Piscataway, NJ: IEEE, 2017: 319−330
[29]	Falk H, Lokuciejewski P. A compiler framework for the reduction of worst-case execution times[J]. Real-Time Systems, 2010, 46: 251−300 doi: 10.1007/s11241-010-9101-x
[30]	Broman D, Zimmer M, Kim Y, et al. Precision timed infrastructure: Design challenges[C/OL]//Proc of the 2013 Electronic System Level Synthesis Conf(ESLsyn). Piscataway, NJ: IEEE, 2013 [2022-08-18].https://ieeexplore.ieee.org/abstract/document/6573221
[31]	Dutt N D. Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs[J]. ACM Transactions on Design Automation of Electronic Systems, 2004, 11(3): 626−658
[32]	Banakar R, Steinke S, Lee B S, et al. Scratchpad memory: Design alternative for cache on-chip memory in embedded systems[C/OL]//Proc of the 10th Int Symp on Hardware/Software Codesign(CODES 2002). Piscataway, NJ: IEEE, 2002 [2022-08-19].https://ieeexplore.ieee.org/abstract/document/1003604
[33]	Rice H G. Classes of recursively enumerable sets and their decision problems[J]. Transactions of the American Mathematical Society, 1953, 74(2): 358−366 doi: 10.1090/S0002-9947-1953-0053041-6
[34]	Kopetz H. Event-triggered versus time-triggered real-time systems[G]//the Operating Systems of the 90s & Beyond, International Workshop. Berlin: Springer, 1991: 86−101
[35]	Kopetz H, Bauer G. The time-triggered architecture[J]. Proceedings of the IEEE, 2003, 91(1): 112−126 doi: 10.1109/JPROC.2002.805821
[36]	Aparicio L C, Segarra J, Rodríguez C, et al. Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems[J]. Journal of Systems Architecture, 2011, 57(7): 695−706 doi: 10.1016/j.sysarc.2010.08.008
[37]	Pont M J. Patterns for Time-Triggered Embedded Systems: Building Reliable Applications with the 8051 Family of Microcontrollers[M]. Boston: Addison Wesley, 2001
[38]	Hughes Z. Design and evaluation of a predictable embedded processor for use in timetriggered applications[D]. Leicester, the UK: University of Leicester, 2010
[39]	Schoeberl M. A Java processor architecture for embedded real-time system[J]. Journal of Systems Architecture, 2008, 54(1): 265−286
[40]	Berry G, Gonthier G. The Esterel synchronous programming language: Design, semantics, implementation[J]. Science of Computer Programming, 1992, 19(2): 87−152 doi: 10.1016/0167-6423(92)90005-V
[41]	Salcic Z, Dong Hui, Roop P S, et al. HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems[J]. Microprocessors and Microsystems, 2006, 30(2): 72−85 doi: 10.1016/j.micpro.2005.05.001
[42]	Salcic Z, Dong Hui, Roop P, et al. REMIC: Design of a reactive embedded microprocessor core[C]//Proc of the 2005 Asia and South Pacific Design Automation Conf. Piscataway, NJ: IEEE, 2005: 977−981
[43]	Yuan S, Andalam S, Yoong L H, et al. STARPro—A new multithreaded direct execution platform for Esterel[J]. Electronic Notes in Theoretical Computer Science, 2009, 238(1): 37−55 doi: 10.1016/j.entcs.2008.01.005
[44]	Wan Bo, Li Xi, Luo Haizhao, et al. Work-in-progress: TTI: A timing ISA for LET model in safety-critical systems[C]//Proc of the 2017 IEEE Real-Time Systems Symp(RTSS). Piscataway, NJ: IEEE, 2017: 363−365
[45]	Henzinger T, Horowitz B, Kirsch C. Giotto: A time-triggered language for embedded programming[J]. Proceedings of the IEEE, 2003, 91(1): 84−99 doi: 10.1109/JPROC.2002.805825
[46]	Lawes J. Car brakes, New Zealand: A Guide to Upgrading, Repair and Maintenance[M]. Marlborough, New Zealand: Crowood Press, 2014
[47]	Bui D, Lee E, Liu I, et al. Temporal isolation on multiprocessing architectures[C]//Proc of the 48th Design Automation Conf. New York: ACM, 2011: 274−279
[48]	Lickly B, Liu I, Kim S, et al. Predictable programming on a precision timed architecture[C]//Proc of the 2008 Int Conf on Compilers, Architectures and Synthesis for Embedded Systems. New York: ACM, 2008: 137−146
[49]	Sarkar A, Mueller F, Ramaprasad H. Static task partitioning for locked caches in multicore real-time systems[J]. ACM Transactions on Embedded Computing Systems, 2015, 14(1): 4: 1−4: 30
[50]	Patterson D A, Hennessy J L. Computer Organization and Design MIPS Edition: The Hardware/Software Interface[M]. 5th ed. San Francisco, CA: Morgan Kaufmann, 2013
[51]	Hassan M, Kaushik A M, Patel H. Predictable cache coherence for multi-core real-time systems[C]//Proc of the 2017 IEEE Real-Time and Embedded Technology and Applications Symp(RTAS). Piscataway, NJ: IEEE, 2017: 235−246
[52]	Kaushik A M, Tegegn P, Wu Zhuanhao, et al. CARP: A data communication mechanism for multi-core mixed-criticality systems[C]//Proc of the 2019 IEEE Real-Time Systems Symp(RTSS). Piscataway, NJ: IEEE, 2019: 419−432
[53]	Wu Zhuanhao, Kaushik A M, Tegegn P, et al. A hardware platform for exploring predictable cache coherence protocols for real-time multicores[C]//Proc of the 27th IEEE Real-Time and Embedded Technology and Applications Symp(RTAS). Piscataway, NJ: IEEE, 2021: 92−104
[54]	Kaushik A M, Hassan M, Patel H. Designing predictable cache coherence protocols for multi-core real-time systems[J]. IEEE Transactions on Computers, 2020, 70(12): 2098−2111
[55]	Paollieri M, Quiñones E, Cazorla F J, et al. Hardware support for WCET analysis of hard real-time multicore systems[C]//Proc of the 36th Annual Int Symp on Computer Architecture. New York: ACM, 2009, 57−58
[56]	Hassan M, Patel H, Pellizzoni R. A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems[C]//Proc of the 21st IEEE Real-Time and Embedded Technology and Applications Symp. Piscataway, NJ: IEEE, 2015: 307−316
[57]	Rosen J, Andrei A, Eles P, et al. Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip[C]//Proc of the 28th IEEE Int Real-Time Systems Symp(RTSS). Piscataway, NJ: IEEE, 2007: 49−60
[58]	Gracioli G, Alhammad A, Mancuso R, et al. A survey on cache management mechanisms for real-time embedded systems[J]. ACM Computing Surveys, 2015, 48(2): 1−36
[59]	王朋宇, 陈云霁, 沈海华, 等. 片上多核处理器存储一致性验证[J]. 软件学报, 2010, 21（4）: 863−874 Wang Pengyu, Chen Yunji, Shen Haihua, et al. Memory consistency verification of chip multi-processor[J]. Journal of Software, 2010, 21(4): 863−874 (in Chinese)
[60]	Lamport L. Time, clocks, and the ordering of events in a distributed system[J]. Communications of the ACM, 1978, 21(7): 558−565 doi: 10.1145/359545.359563