A Load Balanced Switch Architecture Based on Implicit Flow Splitter

In order to solve the problems of high computation complexity, PHOL (pseudo head of line) blocking, etc. in Byte-Focal switches, this paper proposes a load balanced switch architecture called LB-IFS (load balanced switch based on implicit Flow Splitter). LB-IFS promotes a DBM (double-buffering mode) and a 2-step scheduling scheme to satisfactorily solve the PHOL problem and ensure that packets of the same flow depart from the first crossbar in the same order as they arrive. Furthermore, the novel IFSs (implicit flow splitters) at the input port assign a TFP (theoretical forwarding paths) for individual cells to be used by output ports. The RB (re-sequencing buffer) organized in VIQ (virtual input queue) structure, in conjunction with TFPs, will ensure that packets can be emitted out of switch without disordering conveniently. Theoretic analysis and simulation results have shown that LB-IFS has better performance than Byte-Focal in delay and ensures the computation complexity of O(1) in the whole switching process.