A High-Performance Variable-Length Instruction Issue Mechanism Based on VLIW Architecture

The variable-length ISA and instruction compression technology can overcome the drawback of traditional very long instruction word (VLIW) architectures. It can address the problem of low density of long instruction word by arranging the instruction word in the instruction cache with high density. However, the instruction compression technology results in separate arrangement of long instruction word into two cache lines, which makes the instruction word cannot be fetched and issued simultaneously and becomes the performance bottleneck of VLIW architecture processors. A novel high-performance variable-length instruction issue window mechanism is proposed in this paper. It solves the instruction fetch and issue problem in separating instruction words. It provides more effective and continuous instruction flow, and temporarily stores one iteration of the loop body to support software pipeline technology, which effectively improves the performance of VLIW DSP processors. By establishing the cycle-accurate processor simulator, simulation experiment is carried out based on DSP/IMG library. Experimental results show that the average performance is improved about 21.89% by adopting the proposed method. Under the TSMC 65nm technology, the area and power of the proposed mechanism increase by 0.98% and 0.76% respectively, compared with that of the core. It is suit able for VLIW architectures that have adopted instruction compression and variable-length ISA technology.