Partial Dynamic Reconfigurable WSN Node with Power and Area Efficiency

WSN can fundamentally change the way of our life. For a WSN system, up to 10000s nodes are expected. Each node needs to be low cost, low power, with reasonal communication and processing capacity. Meanwhile, FPGAs are demonstrated as an approach to improve processing performance efficiently. Conventionally, in embedded system design like WSN, mainly due to the limitation of energy budget, the inclusion of reconfigurable HW is considered as unacceptable. However, FPGA can not only permit static configurability in field, but also enable partial dynamic configurability (PDR) remotely. Both power and area can be saved through mapping different hardcores to one certain chip area. Futhermore, by implemeing PDR technique, each node can be maintained during its lifetime remotely. All those characteristics are demanding in WSN. As a result, it becomes the author's interest to investigate the feasibility of FPGA for WSN. In this paper, a prototype and related design flow are presented and several test cases are used to evaluate the cost of PDR. Finally, it is demonstrated 60% less power cost with 27% area saving.