A Fast Algorithm for Leakage Power Reduction by Input Vector Control

As IC technologies evolve, leakage current is increased exponentially with transistor threshold voltages reduced to maintain adequate performance and noise margins. As a result, leakage power will dominate total power dissipation soon. The stack effect of CMOS transistors makes leakage power different when different input vectors are applied. Input vector control is an effective method when a circuit enters sleep mode. It becomes critical to find a vector that minimizes leakage power to be statically applied to the primary inputs of a circuit. In order to evaluate various algorithms, a gate-level combinational circuit simulator is developed. An algorithm based on probabilities propagation is presented. Experimental results on ISCAS85 benchmark and Godson CPU show that this algorithm can accelerate calculation over triply with acceptable accuracy (error rate about 0.14%).