Lossless Configuration Bitstream Compression for Virtex FPGAs

With the drastical improvements of FPGA's density and performance, the size of the configuration bitstreams has also increased considerably. Therefore, configuration time of FPGA is increasingly becoming a concern, and the memory required for storing various FPGA configuration bitstreams will significantly affect the cost of FPGA-based embedded systems. In this paper, an adaptive LZW algorithm is proposed for compressing the Virtex FPGAs' configuration bitstreams based on detailed analysis of their data regularities. The required decompression hardware is simple. Using this technique, it is demonstrated up to 45.63% compression rate for configuration bitstreams of several real-world applications.