Lossless Configuration Bitstream Compression for Virtex FPGAs

Gu Haiyun; Li Li; Xu Juyan; Gao Minglun

Journal of Computer Research and Development > 2006 > 43(5): 940-945.

Gu Haiyun, Li Li, Xu Juyan, Gao Minglun. Lossless Configuration Bitstream Compression for Virtex FPGAs[J]. Journal of Computer Research and Development, 2006, 43(5): 940-945.

Citation:

Gu Haiyun, Li Li, Xu Juyan, Gao Minglun. Lossless Configuration Bitstream Compression for Virtex FPGAs[J]. Journal of Computer Research and Development, 2006, 43(5): 940-945.

Citation:

Gu Haiyun, Li Li, Xu Juyan, Gao Minglun. Lossless Configuration Bitstream Compression for Virtex FPGAs[J]. Journal of Computer Research and Development, 2006, 43(5): 940-945.

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Lossless Configuration Bitstream Compression for Virtex FPGAs

1(Department of Electronics, Southeast University, Nanjing 210096) 2(Department of Physics, Nanjing University, Nanjing 210093)

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Published Date: May 14, 2006

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Abstract

Abstract

With the drastical improvements of FPGA's density and performance, the size of the configuration bitstreams has also increased considerably. Therefore, configuration time of FPGA is increasingly becoming a concern, and the memory required for storing various FPGA configuration bitstreams will significantly affect the cost of FPGA-based embedded systems. In this paper, an adaptive LZW algorithm is proposed for compressing the Virtex FPGAs' configuration bitstreams based on detailed analysis of their data regularities. The required decompression hardware is simple. Using this technique, it is demonstrated up to 45.63% compression rate for configuration bitstreams of several real-world applications.
- Virtex FPGA,
- configuration bitstream compression,
- LZW algorithm

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