An AVS HDTV Video Decoder Architecture Based on HW/SW Partitioning

Video decoder architecture is developing from dedicated hardware to HW/SW partition, this owes to the powerful process of hardware and the flexibility and programmability of software. The increasing complexity of AVS algorithms has raised the challenge for HW/SW partitioning architecture. In this paper, AVS algorithms and complexity are first analyzed. Based on the analysis, an optimized real-time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder with HW/SW portioning is proposed. It can support real-time AVS JiZhun profile 6.0 level video decoding, and also support flexible A/V synchronization, error recovery, buffer management and system control mechanism. A hardware implementation of the MB level 7-stage synchronized pipeline is selected. The software tasks are realized with a 32-bit RISC processor. Under the control of the RSIC processor, the design can support AVS video syntax extension and revision in the future. The AVS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip AVS HDTV real-time decoder. At 148.5MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 f/s or 1080i@60 field/s) bit-streams. Finally, the decoder chip has been physically implemented in AVS101 on a 6-metal 0.18μm SMIC CMOS technology and fully tested on a prototyping board.