Research on Reliability Evaluation of Cache Based on Instruction Behavior

Soft error arises from the strike of high-energy particle, and does great harm to the reliability of processor. Furthermore, with the change of design targets of processor to low power consumption, high performance, and the reduction of supplying voltage, the occurrence possibility of soft error arises greatly. As a result, research on reliability of processor receives much more attention than ever. Aiming at solving the problem of low efficiency of traditional evaluation methods, which mostly apply fault-injection methods, this paper presents a systematic evaluation method of the indispensable memory unit in processor, cache. It takes an evaluation attribute, architectural vulnerability factor as research object. On the one hand, this method analyzes instructions that have no impact on the final execution result of application program to get the instructions that affect AVF. On the other hand, according to memory type, writing policy, and features of data/instruction and address tag array of cache, it analyzes various combination of neighboring operations' effects on AVF, thus attaining the needed information in AVF evaluation process. In the experiment, architectural vulnerability factor evaluation of instruction array of cache in PISA architecture is performed. The experiment results demonstrate the validity of this method.