A 2D-Cache Based Memory Bandwidth Optimization Method for H.264 Motion Compensation

Motion compensation(MC) consumes a lot of external memory bandwidth during H.264/AVC video decoding, which becomes a significant bottleneck of high definition(HD) H.264/AVC video codec design. Analytical results show that such significant bandwidth consumption comes from five parts: pixel data reload, address alignment, burst access, SDRAM page precharge/active and conflict memory accesses. In view of this, a 2D-cache based MC bandwidth optimization method is proposed. By exploiting pixel data reuse, such optimization method avoids large numbers of data reloading. Through the combination with SDRAM data mapping optimization, it integrates many short random accesses to some address aligned burst accesses, and at the same time reduces the page precharge/active frequency. In addition, a memory access group burst mode is proposed to reduce the bandwidth consumption caused by the conflict SDRAM access. Experimental results show that the new method reduces 82.9%-87.6% of the MC memory bandwidth, and it demonstrates a further reduction of 64%-87% of the bandwidth consumption compared with some existing high optimization efficiency methods. Provided the same amount of bandwidth reduction, the circuit area of the new method is reduced by 91% compared with the traditional cache architecture. The method proposed in this paper has been applied in a multimedia SoC chip.