Parallel Modeling for Line Speed Approximate Content-Based Packet Classification

A parallel and pipeline hardware scheme is proposed for approximate content-based packet classification, which is scalable for large rule set and high-speed network rate. With the employment of configurable window unit, the error level of approximate matching can be flexibly adjusted. Furthermore, various kinds of approximate matching errors (insertion, deletion, substitution, transposition) can be detected with different structures of rule combination unit. A probability model of packet matched is also proposed for large alphabet (Chinese char) environment, which proves that the hardware scheme is practicable.