nPSA：A Low-Latency, Deterministic Switching Architecture for TSN Chips

Time-sensitive networking (TSN) guarantees the real-time and determinism for critical traffic through spatio-temporal resource planning. The planning tool uses the maximum switching delay of each chip under heavy load as input parameters when allocating temporal resources. In order to satisfy the low-delay requirement of TSN applications, the TSN chip designers are supposed to minimize the maximum switching delay as an important goal. Current commercial TSN chips generally adopt a single-pipeline switching architecture, which is prone to “complete frame blocking” at the entrance of the pipeline, resulting that it is hard to reduce the maximum switching delay. Therefore, we propose a multi-pipeline switching architecture named nPSA based on time division multiplexing mechanism, which optimizes the “complete frame blocking” into a “slice blocking” problem. Moreover, the weighted round-robin slot allocation algorithm (WRRSA) is proposed for the time division multiplexing mechanism to calculate the slot allocation scheme under different port types. At present, the nPSA architecture and WRRSA algorithm have been applied in the OpenTSN open-source chip and the “HX-DS09” ASIC chip. The actual test results show that the maximum switching delay time experienced by the 64B critical frame in the OpenTSN chip and the “HX-DS09” chip are 1648ns and 698ns, respectively. Compared with the theoretical value are the TSN switching chip designed based on the single-pipeline architecture, the delay value are reduced by about 88% and 95% respectively.