nPSA：A Low-Latency, Deterministic Switching Architecture for TSN Chips

Fu Wenwen; Liu Rulin; Quan Wei; Jiang Xuyan; Sun Zhigang

doi:10.7544/issn1000-1239.202111205

Journal of Computer Research and Development > 2023 > 60(6): 1322-1336. > DOI: 10.7544/issn1000-1239.202111205

Fu Wenwen, Liu Rulin, Quan Wei, Jiang Xuyan, Sun Zhigang. nPSA：A Low-Latency, Deterministic Switching Architecture for TSN Chips[J]. Journal of Computer Research and Development, 2023, 60(6): 1322-1336. DOI: 10.7544/issn1000-1239.202111205

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nPSA：A Low-Latency, Deterministic Switching Architecture for TSN Chips

1.
College of Computer Science and Technology, National University of Defense Technology, Changsha 410073
2.
Science and Technology on Parallel and Distributed Processing Laboratory (National University of Defense Technology), Changsha 410073

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Author Bio:
Fu Wenwen: born in 1994. PhD, assistant professor. His main research interests include programmable network and time-sensitive network

Liu Rulin: born in 1989. PhD, assistant professor. His main research interests include network architecture and related IC design

Quan Wei: born in 1987. PhD, associate professor. His main research interests include time-sensitive network, software defined network and FPGA design

Jiang Xuyan: born in 1998.PhD candidate. Her main research interests include traffic planning and task scheduling in time-sensitive network

Sun Zhigang: born in 1974. PhD, professor. His main research interests include software defined network, time-sensitive network, network architecture, FPGA design and network security
Received Date: December 06, 2021
Revised Date: June 26, 2022
Available Online: February 26, 2023

Graphical Abstract

Abstract

Abstract

Time-sensitive networking (TSN) guarantees the real-time and determinism for critical traffic through spatio-temporal resource planning. The planning tool uses the maximum switching delay of each chip under heavy load as input parameters when allocating temporal resources. In order to satisfy the low-delay requirement of TSN applications, the TSN chip designers are supposed to minimize the maximum switching delay as an important goal. Current commercial TSN chips generally adopt a single-pipeline switching architecture, which is prone to “complete frame blocking” at the entrance of the pipeline, resulting that it is hard to reduce the maximum switching delay. Therefore, we propose a multi-pipeline switching architecture named nPSA based on time division multiplexing mechanism, which optimizes the “complete frame blocking” into a “slice blocking” problem. Moreover, the weighted round-robin slot allocation algorithm (WRRSA) is proposed for the time division multiplexing mechanism to calculate the slot allocation scheme under different port types. At present, the nPSA architecture and WRRSA algorithm have been applied in the OpenTSN open-source chip and the “HX-DS09” ASIC chip. The actual test results show that the maximum switching delay time experienced by the 64B critical frame in the OpenTSN chip and the “HX-DS09” chip are 1648ns and 698ns, respectively. Compared with the theoretical value are the TSN switching chip designed based on the single-pipeline architecture, the delay value are reduced by about 88% and 95% respectively.
- time-sensitive networking,
- switching architecture,
- maximum switching delay,
- time division multiplexing,
- multi-pipelines,
- slot allocation algorithm

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References (23)

References

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