A New Analysis Model for Task Buffer of Pipeline Simulator Based on Queueing Network

Pipeline simulator of software is a key technology in software simulation of embedded microprocessors. A new analysis model for the pipeline simulator of the embedded SPARC-V8 microprocessor is proposed, and the associated analysis method for software simulation is also given. Specifically, the queueing network model with M/M/1/N queues is applied to analyze the task arrival and service blocking in the task buffer size of the pipeline simulator. To analyze the blocking phenomenon of pipeline stage, the “holding nodes” are added to the original model and hence obtain an equivalent model that is easy for blocking analysis. The evaluation indices of system performance are calculated by using an iterative algorithm with approximate calculation. The relationship curves between system throughput and task buffer size are established according to the system evaluation indices. The task buffer size values for each functional module for pipeline simulator are obtained by the change trend of curve. The actual buffer size of the pipeline simulator can be set by the calculated values from our model. The experiments show that the data obtained from the model are consistent with the actual operating data. Thus, the new model and the proposed analysis method have important guiding significance for optimizing the performance of the pipeline simulator.