Citation: | Yu Zihao, Chen Lu, Sun Ninghui, Bao Yungang. Quality Optimization Method of Dynamic Binary Translation Code Targeting for RISC-V[J]. Journal of Computer Research and Development, 2023, 60(10): 2322-2334. DOI: 10.7544/issn1000-1239.202220296 |
Dynamic binary translation is a mainstream technology to solve the problem of an instruction set facing ecological barriers. By translating the binary program of the source instruction set into the target instruction set, the application program of the source instruction set can be run on the processor of the target instruction set. A major challenge of dynamic binary translation technology is how to generate high-quality target instruction sequences, especially when there are differences between the source instruction sets and the target instruction sets. In order to explore this problem, We take RISC-V64 instruction set as the target instruction, and analyze the factors that affect the translation quality of dynamic binary translation technology when RISC-V64, RISC-V32, MIPS32 and x86 are used as source instructions respectively. In view of these factors, We propose corresponding optimization methods, and improve the translation quality with the help of some instructions in RISC-V B extension and P extension. Finally, We propose a new dynamic binary translation program DBT-FEMU and implement the above optimization technique, DBT-FEMU is evaluated in the simulator and FPGA. The evaluation data show that when running the SPEC CPU2006 integer benchmark, the above optimization techniques can reduce the number of dynamic instructions executed by the target program by an average of 57%, and the average performance of the translated target program is 4.12 times that of QEMU-i386.
[1] |
Debian Community. RISC-V port of Debian [EB/OL]. (2022-03-24)[2022-04-11].https://wiki.debian.org/RISC-V
|
[2] |
Henning J. SPEC CPU2006 benchmark descriptions[J]. ACM SIGARCH Computer Architecture News, 2006, 34(4): 1−17 doi: 10.1145/1186736.1186737
|
[3] |
RISC-V Community. RISC-V bit-manipulation ISA-extensions [EB/OL]. (2022-01-21)[2022-04-11].https://github.com/riscv/riscv-bitmanip
|
[4] |
RISC-V Community. RISC-V "P" extension proposal [EB/OL]. (2022-03-30)[2022-04-11].https://github.com/riscv/riscv-p-spec
|
[5] |
Klaiber A. The technology behind Crusoe processors [R/OL]. Santa Clara, CA: Transmeta Corporation, 2000[2022-04-11]. http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf
|
[6] |
Cmelik B, Keppel D. Shade: A fast instruction-set simulator for execution profiling [C] //Proc of the 1994 ACM SIGMETRICS Conf on Measurement and Modeling of Computer Systems. New York: ACM, 1994: 128−137
|
[7] |
Dehnert C, Grant K, Banning P, et al. The transmeta code morphing software: Using speculation, recovery, and adaptive retranslation to address real-life challenges [C] //Proc of the 2003 Int Symp on Code Generation and Optimization. Piscataway, NJ: IEEE, 2003: 15−24
|
[8] |
Chernoff A, Herdeg M, Hookway R, et al. Fx! 32: A profile-directed binary translator[J]. IEEE Micro, 1998, 18(2): 56−64 doi: 10.1109/40.671403
|
[9] |
Ebcioğlu K, Altman E. Daisy: Dynamic compilation for 100% architectural compatibility [C] //Proc of the 24th Annual Int Symp on Computer Architecture. New York: ACM, 1997: 26−37
|
[10] |
Gschwind M, Altman E, Sathaye S, et al. Dynamic and transparent binary translation[J]. Computer, 2000, 33(3): 54−59 doi: 10.1109/2.825696
|
[11] |
Kotzmann T, Wimmer C, Mössenböck H, et al. Design of the Java hotspot™ client compiler for Java 6[J]. ACM Transactions on Architecture and Code Optimization, 2008, 5(1): 1−32
|
[12] |
Zheng C, Thompson C. PA-RISC to IA-64: Transparent execution, no recompilation[J]. Computer, 2000, 33(3): 47−52 doi: 10.1109/2.825695
|
[13] |
Ung D, Cifuentes C. Machine-adaptable dynamic binary translation[J]. ACM SIGPLAN Notices, 2000, 35(7): 41−51 doi: 10.1145/351403.351414
|
[14] |
Tröger J. Specification-driven dynamic binary translation [D]. Brisbane, Australia: Queensland University of Technology, 2005
|
[15] |
Bellard F. QEMU, a fast and portable dynamic translator [C] //Proc of the 2nd USENIX Annual Technical Conf. Berkeley, CA: USENIX Association, 2005: 41−46
|
[16] |
Anthony L. Announce: Release 0.10. 0 of QEMU [EB/OL]. (2009-03-04)[2022-04-11].https://lists.gnu.org/archive/html/qemu-devel/2009-03/msg00154.html
|
[17] |
傅立国,庞建民,王军,等. 动态二进制翻译中库函数处理的优化[J]. 计算机研究与发展,2019,56(8):1783−1791 doi: 10.7544/issn1000-1239.2019.20170871
Fu Liguo, Pang Janmin, Wang Jun, et al. Optimization of library function disposing in dynamic binary translation[J]. Journal of Computer Research and Development, 2019, 56(8): 1783−1791 (in Chinese) doi: 10.7544/issn1000-1239.2019.20170871
|
[18] |
李战辉,刘畅,孟建熠,等. 基于高速缓存负荷均衡的动态二进制翻译研究[J]. 计算机研究与发展,2015,52(9):2105−2113 doi: 10.7544/issn1000-1239.2015.20140220
Li Zhanhui, Liu Chang, Meng Jianyi, et al. Cache load balancing oriented dynamic binary translation[J]. Journal of Computer Research and Development, 2015, 52(9): 2105−2113 (in Chinese) doi: 10.7544/issn1000-1239.2015.20140220
|
[19] |
Clark M, Bruce H. Rv8: A high performance RISC-V to x86 binary translator [C/OL] //Proc of the 1st Workshop on Computer Architecture Research with RISC-V (CARRV). 2017[2022-04-11].https://anarch128.org/~mjc/rv8-carrv.pdf
|
[20] |
Ilbeyi B, Derek L, Christopher B. Pydgin for RISC-V: A fast and productive instruction-set simulator [C/OL]//Proc of the 3rd RISC-V Workshop. 2016[2022-04-11].https://people.ece.cornell.edu/berkin/ilbeyi-pydgin-riscv2016.pdf
|
[21] |
Guo Xuan, Mullins R. Accelerate cycle-level full-system simulation of multi-core RISC-V systems with binary translation [J]. arXiv preprint, arXiv: 2005.11357, 2020
|
[22] |
Marshall B, Daniel P, Thinh P. Implementing the draft RISC-V scalar cryptography extensions [C/OL] //Proc of the 2020 Hardware and Architectural Support for Security and Privacy. New York: ACM, 2020[2022-04-11].https://dl.acm.org/doi/abs/10.1145/3458903.3458904
|
[23] |
Marshall B, Daniel P, Thinh P. A lightweight ISE for ChaCha on RISC-V [C] //Proc of the 32nd IEEE Int Conf on Application-specific Systems, Architectures and Processors (ASAP). Piscataway, NJ: IEEE, 2021: 25−32
|
[24] |
Babu S, Snehashri S, Deepa S, et al. Evaluation of bit manipulation instructions in optimization of size and speed in RISC-V [C] //Proc of the 34th Int Conf on VLSI Design (VLSID). Piscataway, NJ: IEEE, 2021: 54−59
|
[25] |
Chen Y, Hui-Hsin L, Chia-Hsuan C, et al. Experiments and optimizations for TVM on RISC-V architectures with P extension [C/OL] //Proc of the 2020 Int Symp on VLSI Design, Automation and Test (VLSI-DAT). Piscataway, NJ: IEEE, 2020[2022-01-11].https://ieeexplore.ieee.org/abstract/document/9196477/
|
[26] |
RISC-V Community. RISC-V calling conventions [EB/OL]. (2022-04-01)[2022-04-11].https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
|
[27] |
Waterman A, Lee Y, Patterson D, et al. The RISC-V instruction set manual, volume I: User-level ISA, version 2, UCB/EECS-2011−62 [R]. Berkeley, CA: University of California, Berkeley, 2011
|
[28] |
RISC-V Community. Spike RISC-V ISA simulator [EB/OL]. (2022-04-09)[2022-04-11].https://github.com/riscv-software-src/riscv-isa-sim
|
[29] |
Zhao J, Korpan B, Gonzalez A, et al. Sonicboom: The 3rd generation Berkeley out-of-order machine [C/OL] //Proc of the 4th Workshop on Computer Architecture Research with RISC-V (CARRV). 2020[2022-04-11]. http://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CARRV2020.pdf
|
[30] |
Xilinx. Zynq UltraScale+ MPSoC [EB/OL]. (2022-04-11)[2022-04-11].https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
|
[1] | Li Nan, Ding Yidong, Jiang Haoyu, Niu Jiafei, Yi Ping. Jailbreak Attack for Large Language Models: A Survey[J]. Journal of Computer Research and Development, 2024, 61(5): 1156-1181. DOI: 10.7544/issn1000-1239.202330962 |
[2] | Chen Xuanting, Ye Junjie, Zu Can, Xu Nuo, Gui Tao, Zhang Qi. Robustness of GPT Large Language Models on Natural Language Processing Tasks[J]. Journal of Computer Research and Development, 2024, 61(5): 1128-1142. DOI: 10.7544/issn1000-1239.202330801 |
[3] | Shu Wentao, Li Ruixiao, Sun Tianxiang, Huang Xuanjing, Qiu Xipeng. Large Language Models: Principles, Implementation, and Progress[J]. Journal of Computer Research and Development, 2024, 61(2): 351-361. DOI: 10.7544/issn1000-1239.202330303 |
[4] | Yang Yi, Li Ying, Chen Kai. Vulnerability Detection Methods Based on Natural Language Processing[J]. Journal of Computer Research and Development, 2022, 59(12): 2649-2666. DOI: 10.7544/issn1000-1239.20210627 |
[5] | Pan Xuan, Xu Sihan, Cai Xiangrui, Wen Yanlong, Yuan Xiaojie. Survey on Deep Learning Based Natural Language Interface to Database[J]. Journal of Computer Research and Development, 2021, 58(9): 1925-1950. DOI: 10.7544/issn1000-1239.2021.20200209 |
[6] | Zheng Haibin, Chen Jinyin, Zhang Yan, Zhang Xuhong, Ge Chunpeng, Liu Zhe, Ouyang Yike, Ji Shouling. Survey of Adversarial Attack, Defense and Robustness Analysis for Natural Language Processing[J]. Journal of Computer Research and Development, 2021, 58(8): 1727-1750. DOI: 10.7544/issn1000-1239.2021.20210304 |
[7] | Pan Xudong, Zhang Mi, Yan Yifan, Lu Yifan, Yang Min. Evaluating Privacy Risks of Deep Learning Based General-Purpose Language Models[J]. Journal of Computer Research and Development, 2021, 58(5): 1092-1105. DOI: 10.7544/issn1000-1239.2021.20200908 |
[8] | Bao Yang, Yang Zhibin, Yang Yongqiang, Xie Jian, Zhou Yong, Yue Tao, Huang Zhiqiu, Guo Peng. An Automated Approach to Generate SysML Models from Restricted Natural Language Requirements in Chinese[J]. Journal of Computer Research and Development, 2021, 58(4): 706-730. DOI: 10.7544/issn1000-1239.2021.20200757 |
[9] | Yu Kai, Jia Lei, Chen Yuqiang, and Xu Wei. Deep Learning: Yesterday, Today, and Tomorrow[J]. Journal of Computer Research and Development, 2013, 50(9): 1799-1804. |
[10] | Che Haiyan, Feng Tie, Zhang Jiachen, Chen Wei, and Li Dali. Automatic Knowledge Extraction from Chinese Natural Language Documents[J]. Journal of Computer Research and Development, 2013, 50(4): 834-842. |