A System-Level Platform with SoC-FPGA for RISC-V Hardware-Software Integration

Qi Le; Chang Yisong; Chen Yuxiao; Zhang Xu; Chen Mingyu; Bao Yungang; Zhang Ke

doi:10.7544/issn1000-1239.202330060

Journal of Computer Research and Development > 2023 > 60(6): 1204-1215. > DOI: 10.7544/issn1000-1239.202330060 CSTR: 32373.14.issn1000-1239.202330060

Qi Le, Chang Yisong, Chen Yuxiao, Zhang Xu, Chen Mingyu, Bao Yungang, Zhang Ke. A System-Level Platform with SoC-FPGA for RISC-V Hardware-Software Integration[J]. Journal of Computer Research and Development, 2023, 60(6): 1204-1215. DOI: 10.7544/issn1000-1239.202330060

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A System-Level Platform with SoC-FPGA for RISC-V Hardware-Software Integration

Qi Le^1,,
Chang Yisong^{1, 2},
Chen Yuxiao^{1, 2},
Zhang Xu^{1, 2},
Chen Mingyu^{1, 2},
Bao Yungang^{1, 2},
Zhang Ke^{1, 2, ,}

1.
State Key Lab of Processors (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190
2.
School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049

Funds: This work was supported by the Strategic Priority Research Program of Chinese Academy of Sciences (XDA0320000, XDA0320300), and the Major Program of the National Natural Science Foundation of China (62090020).

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Author Bio:
Qi Le: born in 1994. Bachelor, assistant engineer. His main research interests include system-level FPGA prototyping and FPGA cloud

Chang Yisong: born in 1985. PhD, associate professor. His main research interests include computer architecture and heterogeneous computing

Chen Yuxiao: born in 1998. Master candidate. His main research interests include hardware design and verification, FPGA debugging, and simulation acceleration

Zhang Xu: born in 1996. PhD candidate. His main research interests include memory disaggregation, distributed shared-memory, and graph computing

Chen Mingyu: born in 1972. PhD, professor. His main research interests include memory architecture, hardware security method of processor, hardware/software optimization on network protocol of data-center

Bao Yungang: born in 1980. PhD, professor. His main research interests include data-center architecture, agile design methodology of processor chips, and ecosystem of open-source processor chips

Zhang Ke: born in 1982. PhD, professor. His main research interests include computer architecture, heterogenous acceleration, and FPGA cloud
Received Date: January 09, 2023
Revised Date: May 03, 2023
Available Online: May 30, 2023

Graphical Abstract

Abstract

Abstract

Building a system-level prototype platform with FPGAs for hardware-software integration of one processor design under test (DUT) is an essential step in pre-silicon evaluations of the processor chip design. In order to meet design requirements of open-source processors based on the emerging open RISC-V instruction set architecture with minimized FPGA development efforts, we propose a system-level platform with a tightly-coupled SoC-FPGA chip for agile hardware-software integration and evaluation of RISC-V DUT processors. In specific, we first elaborate the interconnect between the DUT and the SoC via the existing SoC-FPGA interfaces. Then we introduce a scheme of virtual inter-processor interrupt to support highly-efficient collaboration between the DUT and the hardcore ARM processor in the SoC-FPGA. As a result, the DUT is able to flexibly leverage various I/O peripherals for full-system evaluation. The hardcore ARM processor is also involved for acceleration of the DUT's time-consuming software workloads. Additionally, we build a configurable framework on cloud for flexible composition and system integration of the DUT's hardware and software components. Based on our evaluation results with a couple of target RISC-V processors, we believe that our proposed platform is of great significance in improving efficiency and shortening iteration period when building a system-level prototype platform.
- pre-silicon system-level platform,
- hardware-software full-system evaluation,
- RISC-V instruction set processor,
- SoC-FPGA

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References (24)

References

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