Promoting Frequency Method for Our Own High Performance Processor Physical Design

He Xiaowei; Yue Daheng; Guo Wei; Sui Bingcai; Deng Quan

doi:10.7544/issn1000-1239.202330942

Journal of Computer Research and Development > 2024 > 61(6): 1429-1435. > DOI: 10.7544/issn1000-1239.202330942 CSTR: 32373.14.issn1000-1239.202330942

He Xiaowei, Yue Daheng, Guo Wei, Sui Bingcai, Deng Quan. Promoting Frequency Method for Our Own High Performance Processor Physical Design[J]. Journal of Computer Research and Development, 2024, 61(6): 1429-1435. DOI: 10.7544/issn1000-1239.202330942

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Promoting Frequency Method for Our Own High Performance Processor Physical Design

College of Computer Science and Technology, National University of Defense Technology, Changsha 410073
Key Laboratory of Advanced Microprocessor Chips and Systems (National University of Defense Technology), Changsha 410073

Funds: This work was supported by the Scientific Research Project of National University of Defense Technology (ZK22-05) and the Specific Technology of Advanced Research for Military Information System Equipments (31513010105).

More Information

Author Bio:
He Xiaowei: born in 1980. PhD, associate research fellow. Member of CCF. His main research interests include physical design of digital and analog integrated circuits, and full custom design of circuits

Yue Daheng: born in 1980. PhD, associate research fellow. His main research interests include physical design of VLSI and high performance computing CPU design

Guo Wei: born in 1986. PhD, assistant research fellow. His main research interests include integrated circuit, microprocessor architecture, and accelerator architecture

Sui Bingcai: born in 1981. PhD, associate research fellow. His main research interest includes microprocessor architecture

Deng Quan: born in 1989. PhD, assistant research fellow. His main research interests include processing in memory and non-volatile memory
Received Date: November 26, 2023
Revised Date: March 05, 2024
Available Online: April 14, 2024

Graphical Abstract

Abstract

Abstract

Promoting core’s frequency is the key method for increasing performance of processor. It is hard to achieve high frequency for processor core by traditional physical design flow. Based on main place and route tools, with the same process, comparable implementation area and power consumption, our own processor core frequency can be promoted by about 30% compared with original design at signoff stage, by employing manually written block netlist, logic and physical design co-optimization, custom routing rule optimization and physical design methodology adjustment.
- place and route,
- co-optimization,
- physical design,
- signoff,
- frequency

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References (12)

References

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