VLSI Implementation of an AES Algorithm Resistant to Differential Power Analysis Attack

Proposed in this paper is a low cost VLSI implementation of an AES algorithm resistant to DPA (differential power analysis) attack using masking. In order to minimize the influence of the modification on the hardware while enabling it to be resistant to DPA, methods such as altering calculation order, module reuse and composite field computation to reduce chip area and maintain its speed are employed. Using the HHNEC 0.25μm CMOS technology, area of the design is about 48(kilo) equivalent gates and its system frequency is up to 70MHz. The through put of the 128bit data encryption and decryption is as high as 380Mbps.