A Low Cost RSA Chip Design Based on CRT

Wu Min, Zeng Xiaoyang, Han Jun, Ma Yongxin, Wu Yongyi, and Zhang Guoquan

Journal of Computer Research and Development > 2006 > 43(4): 639-645.

Wu Min, Zeng Xiaoyang, Han Jun, Ma Yongxin, Wu Yongyi, and Zhang Guoquan. A Low Cost RSA Chip Design Based on CRT[J]. Journal of Computer Research and Development, 2006, 43(4): 639-645.

Citation:

Wu Min, Zeng Xiaoyang, Han Jun, Ma Yongxin, Wu Yongyi, and Zhang Guoquan. A Low Cost RSA Chip Design Based on CRT[J]. Journal of Computer Research and Development, 2006, 43(4): 639-645.

Citation:

Wu Min, Zeng Xiaoyang, Han Jun, Ma Yongxin, Wu Yongyi, and Zhang Guoquan. A Low Cost RSA Chip Design Based on CRT[J]. Journal of Computer Research and Development, 2006, 43(4): 639-645.

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A Low Cost RSA Chip Design Based on CRT

Wu Min, Zeng Xiaoyang, Han Jun, Ma Yongxin, Wu Yongyi, and Zhang Guoquan

(State Key Laboratory of ASIC & System, Fudan University, Shanghai 200433)

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Published Date: April 14, 2006

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Abstract

Abstract

In this paper, a VLSI design and ASIC implementation of a pretty low cost RSA cryptosystem is presented, which is based on the modified Montgomery algorithm and the Chinese remainder Theory (CRT), By adopting a novel scheduling method, we realize 1152-bit modular exponentiation with 576-bit modular multiplier unit, which reduces the hardware complexity greatly. And by using the CRT technique, a comparable throughput with general 1024-bit RSA cryptosystem is achieved. The experimental result shows that a 1024-bit modular exponentiation calculation can be performed in about 1.2 mega cycles, and less than 54K gates are needed. With 40MHz system clock, a signature rate of over 30Kbps can be achieved.
- modified Montgomery algorithm,
- RSA,
- CRT,
- VLSI,
- digital signature

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