An HD Video Motion Estimation Coprocessor Supporting Multiple Coding Standards

Motion estimation is one of the most important parts of video coding standards, and it can remove most of temporal redundancy. In order to satisfy the real-time computational complexity and the flexibility requirement of motion estimation, a motion estimation coprocessor supporting multiple coding standards for real-time high definition video is presented in this paper. The motion estimation coprocessor is designed based on very long instruction words architecture, and can effectively perform various motion estimation algorithms. In the proposed hardware architecture, a two-dimension data-reused processing element array, an SAD tree structure, and a multiple modes cost comparator are employed. The processing element array and the SAD tree structure can efficiently meet the huge computational complexity of motion estimation, and the multiple modes cost comparator is used to support different block partition modes of various video coding standards. With a 0.13 μm CMOS technology, the coprocessor is implemented with 145.5 K gates and 4.25 KB memory at 550 MHz. For validating the proposed hardware architecture and evaluating the performance, a fast full search algorithm modified from the H.264 reference software JM10.2 is performed on it. The experimental results show that when encoding high definition video sequences with 1 920×1 080 frame size and 32×32 search window, the frame rate is up to 60 fps.