Adaptive Buffer Management for Leakage Power Optimization in NoC Routers

Network on chip (NoC) is becoming a promising design solution for interconnection between processor cores and cache banks in CMP (chip multi-processors) as the number cores on a chip increase. Interconnect network is the main power consumption component in CMP. Input buffer is the largest leakage power consumer in DVOQR (dynamic virtual output queues router), and it consumes about 64.9% of the total router leakage power. The run time power gating is one of the attractive methods to reduce the leakage power of routers. The fraction of input buffers can be turned on/off to reduce the leakage power of buffers in adaptive buffer management strategy proposed in this paper, according to the traffic in network. The wakeup latency will lead to the average network latency increase. The look-ahead wakeup technology can hide the wakeup latency and decrease the negative effect. The average network latency is not affected by the wakeup latency in the two-entry-buffer-never-turned-off strategy under low offered traffic rate. Simulation results display that the reduction of leakage power consumed by buffers is up to 46% when offered traffic rate is 0.7 and that the increase of average network latency is as much as 3.8% in two-entry-buffer-never-turned-off strategy when the offered traffic rate is less than 0.4.