A Test Compression Scheme Based on LFSR Reseeding and Optimized Coding

The high density and large-scale IC meets lots of problems during testing, such as huge amount of test data, excessive test power dissipation and so on. This paper presents a scheme of test data compression, which optimizes a set of deterministic test cubes by encoding approach before using linear feedback shift register (LFSR) reseeding. The deterministic test set is obtained by using an automatic test pattern generation (ATPG) software. The test set is compressed to a seed set and stored in ROM on the chip. In the process of compression, firstly, a few specified bits are used to encode partial test cubes for enhancing the consistency between adjacent bits of the cube. This process is aimed at reducing test power. Secondly, in order to improve the encoding efficiency of test compression and even further reduce test storage, the test cubes are encoded to new test cubes by compatible block code (CBC). Finally, the new test cubes are compressed to LFSR seeds. The specified bits in test set encoded with CBC are much less than the original deterministic test set, so the number of stages in LFSR is reduced. Experimental results on ISCAS-89 benchmark show that the scheme can not only reduce test power but also increase the encoding efficiency.